Datasheet
78K0/Ix2 CHAPTER 24 OPTION BYTE
R01UH0010EJ0500 Rev.5.00 648
Feb 28, 2012
Figure 24-1. Format of Option Byte (1/3)
Address: 0080H/1080H
Note
7 6 5 4 3 2 1 0
0 WINDOW1 WINDOW0 WDTON WDCS2 WDCS1 WDCS0 LSROSC
WINDOW1 WINDOW0 Watchdog timer window open period
0 0 25%
0 1 50%
1 0 75%
1 1 100%
WDTON Operation control of watchdog timer counter/illegal access detection
0 Counter operation disabled (counting stopped after reset), illegal access detection operation
disabled
1 Counter operation enabled (counting started after reset), illegal access detection operation enabled
WDCS2 WDCS1 WDCS0 Watchdog timer overflow time
0 0 0 2
7
/fIL (3.88 ms)
0 0 1 2
8
/fIL (7.76 ms)
0 1 0 2
9
/fIL (15.52 ms)
0 1 1 2
10
/fIL (31.03 ms)
1 0 0 2
12
/fIL (124.12 ms)
1 0 1 2
14
/fIL (496.48 ms)
1 1 0 2
15
/fIL (992.97 ms)
1 1 1 2
17
/fIL (3.97 s)
LSROSC Internal low-speed oscillator operation
0 Can be stopped by software (stopped when 1 is written to bit 1 (LSRSTOP) of RCM register)
1 Cannot be stopped (not stopped even if 1 is written to LSRSTOP bit)
Note Set a value that is the same as that of 0080H to 1080H because 0080H and 1080H are switched during the boot
swap operation.
Cautions 1. The combination of WDCS2 = WDCS1 = WDCS0 = 0 and WINDOW1 = WINDOW0 = 0 is prohibited.
2. The watchdog timer continues its operation during self-programming and EEPROM emulation of the
flash memory. During processing, the interrupt acknowledge time is delayed. Set the overflow
time and window size taking this delay into consideration.
3. If LSROSC = 0 (oscillation can be stopped by software), the count clock is not supplied to the
watchdog timer in the HALT and STOP modes, regardless of the setting of bit 0 (LSRSTOP) of the
Internal oscillation mode/PLL control register (RCM).
When 8-bit timer H1 operates with the internal low-speed oscillation clock, the count clock is
supplied to 8-bit timer H1 even in the HALT/STOP mode.
4. Be sure to clear bit 7 to 0.
Remarks 1. f
IL: Internal low-speed oscillation clock frequency
2. ( ): f
IL = 33 kHz (MAX.)