Datasheet
78K0/Ix2 CHAPTER 22 LOW-VOLTAGE DETECTOR
R01UH0010EJ0500 Rev.5.00 636
Feb 28, 2012
Figure 22-4. Timing of Low-Voltage Detector Internal Reset Signal Generation (LVISTART = 0)
<1>
<3>
<4>
<5>
<6>
Internal reset signal
Set LVI to be
used for reset
Supply voltage (V
DD
)
LVIMK flag
(set by software)
Time
LVION flag
(set by software)
Not
cleared
Not cleared
Not
cleared
Not cleared
Wait time
<2>
Cleared
Cleared
Cleared
LVIF flag
LVIMD flag
(set by software)
LVIRF flag
Note 3
LVI reset signal
Cleared by
software
Cleared by
software
POC reset signal
Note 2
V
LVI
V
PDR
= 1.59 V (TYP.)
V
POR
= 1.61 V (TYP.)
H
Note 1
Notes 1. The LVIMK flag is set to “1” by reset signal generation.
2. The LVIIF flag of the interrupt request flag registers and the LVIF flag may be set (1).
3. LVIRF is bit 0 of the reset control flag register (RESF). For details of RESF, refer to CHAPTER 20 RESET
FUNCTION.
Remarks 1. <1> to <6> in Figure 22-4 above correspond to <1> to <6> in the description of “When starting
operation” in 22.4.1 (1) When LVI default start function stopped is set (LVISTART = 0).
2. V
POR: POC power supply rise detection voltage
VPDR: POC power supply fall detection voltage