Datasheet

78K0/Ix2 CHAPTER 22 LOW-VOLTAGE DETECTOR
R01UH0010EJ0500 Rev.5.00 632
Feb 28, 2012
Figure 22-2. Format of Low-Voltage Detection Register (LVIM)
<0>
LVIF
<1>
LVIMD
2
0
3
0
4
0
5
0
6
0
<7>
LVION
Symbol
LVIM
Address: FFBEH After reset: 00H
Note 1
R/W
Note 2
LVION
Notes 3,
4
Enables low-voltage detection operation
0 Disables operation
1 Enables operation
LVIMD
Note 3
Low-voltage detection operation mode (interrupt/reset) selection
0
Generates an internal interrupt signal when the supply voltage (V
DD) drops lower than the
LVI detection voltage (V
LVI) (VDD < VLVI) or when VDD becomes VLVI or higher (VDD  VLVI).
1
Generates an internal reset signal when the supply voltage (V
DD) < the LVI detection
voltage (V
LVI) and releases the reset signal when VDD  VLVI.
LVIF Low-voltage detection flag
0
Supply voltage (V
DD)  LVI detection voltage (VLVI), or when LVI operation is disabled
1
Supply voltage (V
DD) < LVI detection voltage (VLVI)
Notes 1. The reset value changes depending on the reset source and the setting of the option byte.
This register is not cleared (00H) by LVI reset (except reset by LVI default start function).
The value of this register is reset to “00H” by other resets.
2. Bit 0 is read-only.
3. LVION and LVIMD are cleared to 0 in the case of a reset other than an LVI reset. These are not cleared
to 0 in the case of an LVI reset.
4. When LVION is set to 1, operation of the comparator in the LVI circuit is started. Use software to wait for
an operation stabilization time (10
 s (MAX.)) from when LVION is set to 1 until operation is stabilized.
After the operation stabilizes, an external input (minimum pulse width: 200  s) of 200  s or more is
required until LVIF is set (1) after the voltage drops to the LVI detection voltage or less.
Cautions 1. To stop LVI, follow either of the procedures below.
 When using 8-bit memory manipulation instruction: Write 00H to LVIM.
 When using 1-bit memory manipulation instruction: Clear LVION to 0.
2. If LVI operation is disabled (clears LVION) when LVI is used in interrupt mode (LVIMD = 0) and
the supply voltage (V
DD) is less than or equal to the detection voltage (VLVI), an interrupt request
signal (INTLVI) is generated and LVIIF may be set to 1.