Datasheet

78K0/Ix2 CHAPTER 21 POWER-ON-CLEAR CIRCUIT
R01UH0010EJ0500 Rev.5.00 628
Feb 28, 2012
21.4 Cautions for Power-on-Clear Circuit
In a system where the supply voltage (V
DD) fluctuates for a certain period in the vicinity of the POC detection voltage
(V
POR, VPDR), the system may be repeatedly reset and released from the reset status. In this case, the time from release of
reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
<Action>
After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a software
counter that uses a timer, and then initialize the ports.
Figure 21-3. Example of Software Processing After Reset Release (1/2)
If supply voltage fluctuation is 50 ms or less in vicinity of POC detection voltage
; Check the reset source
Note 2
Note 1
Reset
Initialization
processing <1>
50 ms has passed?
(TMIFH1 = 1?)
Initialization
processing <2>
Setting 8-bit timer H1
(to measure 50 ms)
; Initial setting for ports,
setting of division ratio of system clock,
such as setting of timer or A/D converter.
Yes
No
Power-on-clear
Clearing WDT
;f
PRS
= Internal high-speed oscillation clock (default)
Set the count clock and compare value so that
INTTMH1 occurs after 50 ms have elapsed.
Timer starts (TMHE1 = 1).
Notes 1. If reset is generated again during this period, initialization processing <2> is not started.
2. A flowchart is shown on the next page.