Datasheet

78K0/Ix2 CHAPTER 21 POWER-ON-CLEAR CIRCUIT
R01UH0010EJ0500 Rev.5.00 627
Feb 28, 2012
Figure 21-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit
and Low-Voltage Detector (2/2)
(2) When LVI is ON upon power application (option byte: LVISTART = 1)
Internal high-speed
oscillation clock (f
IH )
High-speed
system clock (f
XH )
(when X1 oscillation
is selected)
Operation
stops
CPU
0 V
Supply voltage
(V
DD )
2.7 V
Note 1
Set LVI to be
used for interrupt
Starting oscillation is
specified by software
Starting oscillation is
specified by software
Starting oscillation is
specified by software
Normal operation
(internal high-speed
oscillation clock)
Note 2
Normal operation
(internal high-speed
oscillation clock)
Note 2
Operation stops
Reset
period
(oscillation
stop)
Normal operation
(internal high-speed
oscillation clock)
Note 2
Reset
period
(oscillation
stop)
Internal reset signal
V PDR = 1.59 V (TYP.)
V
LVI
V POR = 1.61 V (TYP.)
V
LVI = 1.91 V (TYP.)
Wait for oscillation
accuracy stabilization
(102 to 407 μs)
Wait for oscillation
accuracy stabilization
(102 to 407 μs)
Wait for oscillation
accuracy stabilization
(102 to 407 μs)
Note 3
POC processing time
(0.93 to 3.7 ms)
Reset processing time
(12 to 51 μs)
Reset processing time
(12 to 51 μs)
Note 3
POC processing time
(0.93 to 3.7 ms)
Reset processing time
(12 to 51 μs)
Set LVI to be
used for reset
Set LVI to be
used for reset
Notes 1. The operation guaranteed range is 2.7 V  VDD  5.5 V. Perform a normal operation after making sure that
the voltage is 2.7 V or more. To make the state at lower than 2.7 V reset state when the supply voltage
falls, use the reset function of the low-voltage detector, or input the low level to the RESET pin.
2. The internal high-speed oscillation clock or high-speed system clock can be selected as the CPU clock. To
use the X1 clock, use the OSTC register to confirm the lapse of the oscillation stabilization time.
3. The following times are required between reaching the POC detection voltage (1.59 V (TYP.)) and starting
normal operation.
 When the time to reach 1.91 V (TYP.) from 1.59 V (TYP.) is less than 3.7 ms:
A POC processing time of about 1.0 to 3.8 ms is required between reaching 1.59 V (TYP.) and starting
normal operation.
 When the time to reach 1.91 V (TYP.) from 1.59 V (TYP.) is greater than 3.7 ms:
A reset processing time of about 12 to 51
 s is required between reaching 1.91 V (TYP.) and starting
normal operation.
Caution Set the low-voltage detector by software after the reset status is released (refer to CHAPTER 22
LOW-VOLTAGE DETECTOR).
Remark V
LVI: LVI detection voltage
VPOR: POC power supply rise detection voltage
V
PDR: POC power supply fall detection voltage