Datasheet

78K0/Ix2 CHAPTER 21 POWER-ON-CLEAR CIRCUIT
R01UH0010EJ0500 Rev.5.00 626
Feb 28, 2012
Figure 21-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit
and Low-Voltage Detector (1/2)
(1) When LVI is OFF upon power application (option byte: LVISTART = 0)
Internal high-speed
oscillation clock (f
IH)
High-speed
system clock (f
XH)
(when X1 oscillation
is selected)
Starting oscillation is
specified by software
Operation
stops
Starting oscillation is
specified by software
CPU
0 V
Supply voltage
(V
DD )
2.7 V
Note 1
0.5 V/ms (MIN.)
Note 2
Starting oscillation is
specified by software
Set LVI to be
used for reset
Set LVI to be
used for reset
Set LVI to be
used for interrupt
Operation stops
Reset
period
(oscillation
stop)
Reset
period
(oscillation
stop)
Normal operation
(internal high-speed
oscillation clock)
Note 4
Internal reset signal
V PDR = 1.59 V (TYP.)
V
LVI
V
POR = 1.61 V (TYP.)
Wait for oscillation
accuracy stabilization
(102 to 407 μs)
Note 3
Wait for oscillation
accuracy stabilization
(102 to 407 μs)
Wait for oscillation
accuracy stabilization
(102 to 407 μs)
Note 3
Reset processing
(12 to 51 μs)
Wait for voltage
stabilization
(0.93 to 3.7 ms)
Reset processing (12 to 51 μs)
Normal operation
(internal high-speed
oscillation clock)
Note 4
Wait for voltage
stabilization
(0.93 to 3.7 ms)
Reset processing
(12 to 51 μs)
Normal operation
(internal high-speed
oscillation clock)
Note 4
Notes 1. The operation guaranteed range is 2.7 V  VDD  5.5 V. Perform a normal operation after making sure that
the voltage is 2.7 V or more. To make the state at lower than 2.7 V reset state when the supply voltage
falls, use the reset function of the low-voltage detector, or input the low level to the RESET pin.
2. If the rate at which the voltage rises to 2.7 V after power application is slower than 0.5 V/ms (MIN.), input a
low level to the RESET pin before the voltage reaches to 2.7 V, or set LVI to ON by default by using an
option byte (option byte: LVISTART = 1).
3. The internal voltage stabilization wait time includes the oscillation accuracy stabilization time of the internal
high-speed oscillation clock.
4. The internal high-speed oscillation clock or high-speed system clock can be selected as the CPU clock. To
use the X1 clock, use the OSTC register to confirm the lapse of the oscillation stabilization time.
Caution Set the low-voltage detector by software after the reset status is released (refer to CHAPTER 22
LOW-VOLTAGE DETECTOR).
Remark V
LVI: LVI detection voltage
VPOR: POC power supply rise detection voltage
V
PDR: POC power supply fall detection voltage