Datasheet

78K0/Ix2 CHAPTER 21 POWER-ON-CLEAR CIRCUIT

R01UH0010EJ0500 Rev.5.00 625

Feb 28, 2012

21.2 Configuration of Power-on-Clear Circuit

The block diagram of the power-on-clear circuit is shown in Figure 21-1.

Figure 21-1. Block Diagram of Power-on-Clear Circuit

−

Reference

voltage

source

Internal reset signal

21.3 Operation of Power-on-Clear Circuit

 An internal reset signal is generated on power application. When the supply voltage (V

DD) exceeds POC detection

voltage (VPOR = 1.61 V 0.09 V), the reset status is released.

Caution If the LVI default function enabled is set by using an option byte, the reset signal is not released

until the supply voltage (VDD) exceeds 1.91 V 0.1 V.

 The supply voltage (V

DD) and POC detection voltage (VPDR = 1.59 V 0.09 V) are compared. When VDD < VPDR, the

internal reset signal is generated.

The timing of generation of the internal reset signal by the power-on-clear circuit and low-voltage detector is shown

below.