Datasheet

78K0/Ix2 CHAPTER 20 RESET FUNCTION
R01UH0010EJ0500 Rev.5.00 620
Feb 28, 2012
Table 20-2. Hardware Statuses After Reset Acknowledgment (2/4)
Hardware Status After Reset
Acknowledgment
Note 1
Clock operation mode select register (OSCCTL) 00H
Processor clock control register (PCC) 01H
Internal oscillation mode/PLL control register (RCM) 80H
Main OSC control register (MOC) 80H
Main clock mode register (MCM) 00H
Oscillation stabilization time counter status register (OSTC) 00H
Oscillation stabilization time select register (OSTS) 05H
16-bit timer X0 operation control registers 0 to 4 (TX0CTL0, TX0CTL1,
TX0CTL2, TX0CTL3, TX0CTL4)
00H
16-bit timer X1 operation control registers 0 to 2, 4 (TX1CTL0, TX1CTL1,
TX1CTL2, TX1CTL4)
00H
16-bit timer X0 output control register 0 (TX0IOC0) 00H
16-bit timer X1 output control register 0 (TX1IOC0) 00H
16-bit timer X0 compare registers 0 to 3 (TX0CR0, TX0CR1, TX0CR2,
TX0CR3)
0000H
16-bit timer X1 compare registers 0 to 3 (TX1CR0, TX1CR1, TX1CR2,
TX1CR3)
0000H
16-bit timer X0 capture/compare register 0 (TX0CCR0) 0000H
16-bit timer X1 capture/compare register 0 (TX1CCR0) 0000H
High-impedance output function enable register (HIZTREN) 00H
High-impedance output mode select register (HIZTRS) 00H
16-bit timers X0, X1
High-impedance output function control register 0 (HZA0CTL0) 00H
16-bit timer counter 00 (TM00) 0000H
16-bit timer capture/compare registers 000, 010 (CR000, CR010) 0000H
16-bit timer mode control register 00 (TMC00) 00H
Prescaler mode register 00 (PRM00) 00H
Capture/compare control register 00 (CRC00) 00H
16-bit timer/event counter
00
16-bit timer output control register 00 (TOC00) 00H
8-bit timer counter 51 (TM51) 00H
8-bit compare register 51 (CR51) 00H
Timer clock selection register 51 (TCL51) 00H
8-bit timer/event counter
51
8-bit timer mode control register 51 (TMC51) 00H
8-bit timer H1 compare registers 01, 11 (CMP01, CMP11) 00H
8-bit timer H1 mode register 1 (TMHMD1) 00H
8-bit timer H1
8-bit timer H1 carrier control register 1 (TMCYC1) 00H
Watchdog timer Watchdog timer enable register (WDTE) 1AH/9AH
Note 2
Notes 1. During reset signal generation or oscillation stabilization time wait, only the PC contents among the hardware
statuses become undefined. All other hardware statuses remain unchanged after reset.
2. The reset value of WDTE is determined by the option byte setting.
Remark The special function registers (SFRs) mounted depend on the product. Refer to 3.2.3 Special function
registers (SFRs).