Datasheet

78K0/Ix2 CHAPTER 20 RESET FUNCTION
R01UH0010EJ0500 Rev.5.00 618
Feb 28, 2012
Table 20-1. Operation Statuses During Reset Period
Item During Reset Period
System clock Clock supply to the CPU is stopped.
fIH Operation stopped
fX Operation stopped (X1 and X2 pins are input port mode)
Main system clock
fEXCLK Clock input invalid (EXCLK pin is input port mode)
fIL
CPU
Flash memory
Operation stopped
RAM
Operation stopped (The value, however, is retained when the voltage is at least the power-on
clear detection voltage.)
Port (latch)
X0 16-bit timer
X1
16-bit timer/event counter 00
8-bit timer/event counter 51
8-bit timer H1
Watchdog timer
A/D converter
Operational amplifier
(AMP, PGA)
Comparators 0 to 2
UART6/DALI
CSI11
Serial interface
IICA
Multiplier
External interrupt
Operation stopped
Power-on-clear function Operable
Low-voltage detection function Operation stopped (however, operation continues at LVI reset)
On-chip debug function Operation stopped
Remarks 1. f
IH: Internal high-speed oscillation clock, fX: X1 clock
f
EXCLK: External main system clock, fIL: Internal low-speed oscillation clock
2. The functions mounted depend on the product. Refer to 1.4 Block Diagram and 1.5 Outline of
Functions.