Datasheet

78K0/Ix2 CHAPTER 20 RESET FUNCTION
R01UH0010EJ0500 Rev.5.00 617
Feb 28, 2012
Figure 20-4. Timing of Reset in STOP Mode by RESET Input
Delay
Normal
operation
Status of CPU
Reset period
(oscillation stop)
RESET
Internal reset signal
STOP instruction execution
Stop status
(oscillation stop)
High-speed system clock
(when X1 oscillation is selected)
Internal high-speed
oscillation clock
Hi-Z
Port pin
Starting X1 oscillation is specified by software.
Normal operation
(internal high-speed oscillation clock)
Reset
processing
Delay
Wait for oscillation
accuracy stabilization
(102 to 407 μs)
(12 to 51 μs)
Remark For the reset timing of the power-on-clear circuit and low-voltage detector, refer to CHAPTER 21 POWER-
ON-CLEAR CIRCUIT and CHAPTER 22 LOW-VOLTAGE DETECTOR.