Datasheet

78K0/Ix2 CHAPTER 20 RESET FUNCTION
R01UH0010EJ0500 Rev.5.00 616
Feb 28, 2012
Figure 20-2. Timing of Reset by RESET Input
Delay Delay
Hi-Z
Normal operationStatus of CPU
Reset period
(oscillation stop)
Normal operation
(internal high-speed oscillation clock)
RESET
Internal reset signal
Port pin
High-speed system clock
(when X1 oscillation is selected)
Internal high-speed
oscillation clock
Starting X1 oscillation is specified by software.
Reset
processing
Wait for oscillation
accuracy stabilization
(102 to 407 μs)
(12 to 51 μs)
Figure 20-3. Timing of Reset Due to Watchdog Timer Overflow
Normal operation
Reset period
(oscillation stop)
Watchdog timer
overflow
Internal reset signal
Hi-Z
Port pin
High-speed system clock
(when X1 oscillation is selected)
Internal high-speed
oscillation clock
Starting X1 oscillation is specified by software.
Normal operation
(internal high-speed oscillation clock)
Reset
processing
Status of CPU
Wait for oscillation
accuracy stabilization
(102 to 407 μs)
(12 to 51 μs)
Caution A watchdog timer internal reset resets the watchdog timer.