Datasheet
78K0/Ix2 CHAPTER 20 RESET FUNCTION
R01UH0010EJ0500 Rev.5.00 614
Feb 28, 2012
CHAPTER 20 RESET FUNCTION
The reset function is mounted onto all 78K0/Ix2 microcontroller products.
The following four operations are available to generate a reset signal.
(1) External reset input via RESET pin
(2) Internal reset by watchdog timer program loop detection
(3) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit
(4) Internal reset by comparison of supply voltage and detection voltage of the low-voltage detector (LVI)
External and internal resets start program execution from the address at 0000H and 0001H when the reset signal is
generated.
A reset is applied when a low level is input to the RESET pin, the watchdog timer overflows, or by POC and LVI circuit
voltage detection, and each item of hardware is set to the status shown in Tables 20-1 and 20-2. Each pin is high
impedance during reset signal generation or during the oscillation stabilization time just after a reset release.
When a low level is input to the RESET pin, the device is reset. It is released from the reset status when a high level is
input to the RESET pin and program execution is started with the internal high-speed oscillation clock after reset
processing. A reset by the watchdog timer is automatically released, and program execution starts using the internal high-
speed oscillation clock (refer to Figures 20-2 to 20-4) after reset processing. Reset by POC and LVI circuit power supply
detection is automatically released when V
DD VPOR or VDD VLVI after the reset, and program execution starts using the
internal high-speed oscillation clock (refer to CHAPTER 21 POWER-ON-CLEAR CIRCUIT and CHAPTER 22 LOW-
VOLTAGE DETECTOR) after reset processing.
Cautions 1. For an external reset, input a low level for 10
s or more to the RESET pin.
(If an external reset is effected upon power application, the period during which the supply
voltage is outside the operating range (V
DD < 2.7 V) is not counted in the 10
s. However, the low-
level input may be continued before POC is released.)
2. During reset signal generation, the X1 clock, internal high-speed oscillation clock, and internal
low-speed oscillation clock stop oscillating. External main system clock input becomes invalid.
3. When the STOP mode is released by a reset, the RAM contents in the STOP mode are held during
reset input. However, because SFR is initialized, the port pins become high-impedance.