Datasheet

78K0/Ix2 CHAPTER 19 STANDBY FUNCTION
R01UH0010EJ0500 Rev.5.00 613
Feb 28, 2012
Figure 19-7. STOP Mode Release by Reset
(1) When high-speed system clock is used as CPU clock
STOP
instruction
Reset signal
High-speed
system clock
(X1 oscillation)
Normal operation
(high-speed
system clock)
STOP mode
Reset
period
Normal operation
(internal high-speed
oscillation clock)
Oscillates
Oscillation
stopped
Oscillates
Status of CPU
Oscillation stabilization time
(2
11
/fX to 2
16
/fX)
Note
Oscillation
stopped
Starting X1 oscillation is
specified by software.
Oscillation stopped
Reset
processing
(12 to 51 μs)
Note Oscillation stabilization time is not required when using the external main system clock (f
EXCLK) as the high-
speed system clock.
Remark fX: X1 clock oscillation frequency
(2) When internal high-speed oscillation clock is used as CPU clock
STOP
instruction
Reset signal
Internal high-speed
oscillation clock
Normal operation
(internal high-speed
oscillation clock)
STOP mode
Reset
period
Normal operation
(internal high-speed
oscillation clock)
Oscillates
Oscillation
stopped
Status of CPU
Oscillates
Oscillation stopped
Reset
processing
(12 to 51 μs)
Wait for oscillation
accuracy stabilization
(102 to 407 μs)
Table 19-4. Operation in Response to Interrupt Request in STOP Mode
Release Source MK PR IE ISP Operation
0 0 0

Next address
instruction execution
0 0 1

Interrupt servicing
execution
0 1 0 1
0 1

0
Next address
instruction execution
0 1 1 1
Interrupt servicing
execution
Maskable interrupt
request
1
  
STOP mode held
Reset
   
Reset processing
: don’t care