Datasheet

78K0/Ix2 CHAPTER 19 STANDBY FUNCTION
R01UH0010EJ0500 Rev.5.00 610
Feb 28, 2012
(2) STOP mode release
Figure 19-5. Operation Timing When STOP Mode Is Released (When Unmasked Interrupt Request Is
Generated)
STOP mode
STOP mode release
High-speed system
clock (X1 oscillation)
High-speed system
clock (external clock
input)
Internal high-speed
oscillation clock
High-speed system
clock (X1 oscillation)
is selected as CPU
clock when STOP
instruction is executed
High-speed system
clock (external clock
input) is selected as
CPU clock when STOP
instruction is executed
Internal high-speed
oscillation clock is
selected as CPU clock
when STOP instruction
is executed
Wait for oscillation
accuracy stabilization
Note 1
HALT status
(oscillation stabilization time set by OSTS)
Clock switched by software
Clock switched by software
High-speed system clock
High-speed system clock
Wait
Note 2
Wait
Note 2
High-speed system clock
Internal high-speed
oscillation clock
Notes 1. The wait time for oscillation accuracy stabilization is as follows:
• RMC register = 00H: 102 to 407
 s
• RMC register = 56H: 120 to 481
 s
2. The wait time is as follows:
• When vectored interrupt servicing is carried out: 17 or 18 clocks
• When vectored interrupt servicing is not carried out: 11 or 12 clocks
The STOP mode can be released by the following two sources.
(a) Release by unmasked interrupt request
When an unmasked interrupt request is generated, the STOP mode is released. After the oscillation stabilization
time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt
acknowledgment is disabled, the next address instruction is executed.