Datasheet

78K0/Ix2 CHAPTER 19 STANDBY FUNCTION
R01UH0010EJ0500 Rev.5.00 606
Feb 28, 2012
(b) Release by reset signal generation
When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset
operation, the program is executed after branching to the reset vector address.
Figure 19-4. HALT Mode Release by Reset
(1) When high-speed system clock is used as CPU clock
HALT
instruction
Reset signal
High-speed
system clock
(X1 oscillation)
HALT mode
Reset
period
Oscillates
Oscillation
stopped
Oscillates
Status of CPU
Normal operation
(high-speed
system clock)
Oscillation stabilization time
(2
11
/f
X
to 2
16
/f
X
)
Note
Normal operation
(internal high-speed
oscillation clock)
Oscillation
stopped
Starting X1 oscillation is
specified by software.
Reset
processing
(12 to 51 μs)
Note Oscillation stabilization time is not required when using the external main system clock (f
EXCLK) as the high-
speed system clock.
(2) When internal high-speed oscillation clock is used as CPU clock
HALT
instruction
Reset signal
Internal high-speed
oscillation clock
Normal operation
(internal high-speed
oscillation clock)
HALT mode
Reset
period
Normal operation
(internal high-speed
oscillation clock)
Oscillates
Oscillation
stopped
Oscillates
Status of CPU
Wait for oscillation
accuracy stabilization
(102 to 407 μs)
Reset
processing
(12 to 51 μs)
Remark f
X: X1 clock oscillation frequency