Datasheet

78K0/Ix2 CHAPTER 18 INTERRUPT FUNCTIONS
R01UH0010EJ0500 Rev.5.00 589
Feb 28, 2012
Figure 18-12. Format of External Interrupt Rising Edge Enable Registers 0, 1 (EGPCTL0, EGPCTL1)
and External Interrupt Falling Edge Enable Registers 0, 1 (EGNCTL0, EGNCTL1) (2/2)
(2) 78K0/IB2
Address: FF48H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
EGPCTL0 EGP7 EGP6 EGP5 EGP4 EGP3 EGP2 EGP1
Note
EGP0
Address: FF49H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
EGNCTL0 EGN7 EGN6 EGN5 EGN4 EGN3 EGN2 EGN1
Note
EGN0
Address: FF4AH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
EGPCTL1 0 0 0 0 0 0 0 EGP8
Address: FF4BH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
EGNCTL1 0 0 0 0 0 0 0 EGN8
EGPn EGNn INTPm and INTCMP0 to INTCMP2 valid edge selection
0 0 Edge detection disabled
0 1 Falling edge
1 0 Rising edge
1 1 Both rising and falling edges
Note 78K0/IB2 (30 pins) only
Caution When using the 78K0/IB2 (30 pins), be sure to clear bits 1 to 7 of EGPCTL1 and EGNCTL1 to
0. When using the 78K0/IB2 (32 pins), be sure to clear bit 1 of EGPCTL0 and EGNCTL0, and
bits 1 to 7 of EGPCTL1 and EGNCTL1 to 0.
Remark n = 0 to 8, m = 0 to 5: 78K0/IB2 (30 pins)
n = 0, 2 to 8, m = 0, 2 to 5: 78K0/IB2 (32 pins)