Datasheet

78K0/Ix2 CHAPTER 18 INTERRUPT FUNCTIONS
R01UH0010EJ0500 Rev.5.00 588
Feb 28, 2012
(5) External interrupt rising edge enable registers 0, 1 (EGPCTL0, EGPCTL1) , external interrupt falling edge
enable registers 0, 1 (EGNCTL0, EGNCTL1)
EGPCTL0, EGPCTL1, EGNCTL0, and EGNCTL1 are the registers that set the INTPm and INTCMP0 to INTCMP2
valid edges.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Remark m = 0, 2 to 4: 78K0/IY2, 78K0/IA2
m = 0 to 5: 78K0/IB2 (30 pins)
m = 0, 2 to 5: 78K0/IB2 (32 pins)
Figure 18-12. Format of External Interrupt Rising Edge Enable Registers 0, 1 (EGPCTL0, EGPCTL1)
and External Interrupt Falling Edge Enable Registers 0, 1 (EGNCTL0, EGNCTL1) (1/2)
(1) 78K0/IY2, 78K0/IA2
Address: FF48H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
EGPCTL0 EGP7 EGP6 0 EGP4 EGP3 EGP2 0 EGP0
Address: FF49H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
EGNCTL0 EGN7 EGN6 0 EGN4 EGN3 EGN2 0 EGN0
Address: FF4AH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
EGPCTL1 0 0 0 0 0 0 0 EGP8
Address: FF4BH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
EGNCTL1 0 0 0 0 0 0 0 EGN8
EGPn EGNn INTPm and INTCMP0 to INTCMP2 valid edge selection
0 0 Edge detection disabled
0 1 Falling edge
1 0 Rising edge
1 1 Both rising and falling edges
Caution Be sure to clear bits 0 and 5 of EGPCTL0 and EGNCTL0, and bits 1 to 7 of EGPCTL1 and
EGNCTL1 to 0 in the 78K0/IY2 and 78K0/IA2.
Remark n = 0, 2 to 4, 6 to 8
m = 0, 2 to 4