Datasheet
78K0/Ix2 CHAPTER 18 INTERRUPT FUNCTIONS
R01UH0010EJ0500 Rev.5.00 584
Feb 28, 2012
(3) Priority specification flag registers (PR0L, PR0H, PR1L, PR1H)
The priority specification flag registers are used to set the corresponding maskable interrupt priority order.
PR0L, PR0H, PR1L, and PR1H are set by a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H, and
PR1L and PR1H are combined to form 16-bit registers PR0 and PR1, they are set by a 16-bit memory manipulation
instruction.
Reset signal generation sets these registers to FFH.
Figure 18-8. Format of Priority Specification Flag Registers (PR0L, PR0H, PR1L) (78K0/IY2)
Address: FFE8H After reset: FFH R/W
Symbol 7 6 <5> <4> <3> 2 <1> <0>
PR0L 1 1 PPR4 PPR3 PPR2 1 PPR0 LVIPR
Address: FFE9H After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> 2 1 0
PR0H TMPR010 TMPR000 TMPRX1 TMPRX0 TMPRH1 1 1 1
Address: FFEAH After reset: FFH R/W
Symbol 7 <6> <5> <4> <3> 2 1 <0>
PR1L 1 CMPPR2 CMPPR1 CMPPR0 TMPR51 1 1 ADPR
XXPRX Priority level selection
0 High priority level
1 Low priority level
Caution Be sure to set bits 2, 6, and 7 of PR0L, bits 0 to 2 of PR0H, and bits 1, 2, and 7 of PR1L to 1.