Datasheet

78K0/Ix2 CHAPTER 18 INTERRUPT FUNCTIONS
R01UH0010EJ0500 Rev.5.00 572
Feb 28, 2012
Table 18-1. Interrupt Source List (1/2)
Interrupt Source IY2 IA2 IB2
Interrupt
Type
Internal/
External
Basic
Configuration
Type
Note 1
Default
Priority
Note
2
Name Trigger
Vector
Table
Address
16
pins
20
pins
30
pins
32
pins
Internal (A) 0 INTLVI Low-voltage detection
Note 3
0004H
1 INTP0 0006H
2 INTP1 0008H
3 INTP2 000AH
4 INTP3 000CH
5 INTP4 000EH
External (B)
6 INTP5
Pin input edge detection
0010H
7 INTSRE6 UART6/DALI reception error generation 0012H
8 INTSR6 End of UART6/DALI reception 0014H
9 INTST6 End of UART6/DALI transmission 0016H
10 INTCSI11 End of CSI11 communication 0018H
11 INTTMH1
Match between TMH1 and CMP01 (when
compare register is specified)
001AH
12 INTTMX0
Match between TMH0CNT and TX0CB1
or TX0CB3 (when compare register is
specified)
001CH
13 INTTMX1
Match between TMH1CNT and TX1CB1
or TX1CB3 (when compare register is
specified)
001EH
14 INTTM000
Match between TM00 and CR000
(when compare register is specified),
TI010 pin valid edge detection
(when capture register is specified)
0020H
15 INTTM010
Match between TM00 and CR010
(when compare register is specified),
TI000 pin valid edge detection
(when capture register is specified)
0022H
16 INTAD End of A/D conversion 0024H
Internal (A)
17
INTTM51
Note 4
Match between TM51 and CR51 (when
compare register is specified)
002AH
18 INTCMP0 Comparator 0 edge detection 002CH
19 INTCMP1 Comparator 1 edge detection 002EH
External (B)
20 INTCMP2 Comparator 2 edge detection 0030H
Maskable
Internal (A) 21 INTIICA0 End of IICA communication 0034H
Notes 1. Basic configuration types (A) to (C) correspond to (A) to (C) in Figure 18-1.
2. The default priority determines the sequence of processing vectored interrupts if two or more maskable
interrupts occur simultaneously. Zero indicates the highest priority and 21 indicates the lowest priority.
3. When bit 1 (LVIMD) of the low-voltage detection register (LVIM) is cleared to 0.
4. When 8-bit timer/event counter 51 is used in the carrier generator mode, an interrupt is generated upon the
timing when the INTTM5H1 signal is generated (refer to Figure 9-13 Transfer Timing).