Datasheet

78K0/Ix2 CHAPTER 17 MULTIPLIER
R01UH0010EJ0500 Rev.5.00 568
Feb 28, 2012
17.2 Configuration of Multiplier
(1) 16-bit higher multiplication result storage register and 16-bit lower multiplication result storage register
(MUL0H, MUL0L)
These two registers, MUL0H and MUL0L, are used to store a 32-bit multiplication result.
In the case of multiplication of 8 bits by 8 bits, the 16 bits of the multiplication result are stored in MUL0L.
In the case of multiplication of 16 bits by 16 bits, the higher 16 bits of the multiplication result are stored in MUL0H
and the lower 16 bits, in MUL0L, so that a total of 32 bits of the multiplication result can be stored.
These registers hold the result of multiplication after the lapse of one CPU clock.
MUL0H and MUL0L can be read by a 16-bit memory manipulation instruction.
Reset signal generation clears these registers to 0000H.
Figure 17-2. Format of 16-bit higher multiplication result storage register and 16-bit lower multiplication result
storage register (MUL0H, MUL0L)
Symbol
Address: FF74H, FF75H After reset: 0000H R
FF75H FF74H
MUL0H
Symbol
Address: FF76H, FF77H After reset: 0000H R
FF77H FF76H
MUL0L