Datasheet

78K0/Ix2 CHAPTER 3 CPU ARCHITECTURE
R01UH0010EJ0500 Rev.5.00 44
Feb 28, 2012
Figure 3-2. Memory Map (  PD78F0741, 78F0743, 78F0745, 78F0751, 78F0753, 78F0755)
FFFFH
FF00H
FEFFH
General-purpose
registers
32 × 8 bits
Special function registers
(SFR)
256 × 8 bits
FEE0H
FEDFH
Internal high-speed RAM
512 × 8 bits
FD00H
FCFFH
Data memory
space
Reserved
Program
memory space
2000H
1FFFH
0000H
Flash memory
8192 × 8 bits
Vector table area
64 × 8 bits
CALLT table area
64 × 8 bits
Option byte area
Note 1
5 × 8 bits
On-chip debug security
ID setting area
Note 1
10 × 8 bits
0800H
07FFH
0040H
003FH
0000H
0085H
0084H
0080H
007FH
008FH
008EH
Program area
1905 × 8 bits
Boot cluster 0
Note 2
Boot cluster 1
1FFFH
1FFFH
1000H
0FFFH
1080H
107FH
1085H
1084H
108FH
108EH
Program area
On-chip debug security
ID setting area
Note 1
10 × 8 bits
Option byte area
Note 1
5 × 8 bits
CALLF entry area
2048 × 8 bits
Program area
Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H, and the on-chip debug security IDs to
0085H to 008EH.
When boot swap is used: Set the option bytes to 0080H to 0084H and 1080H to 1084H, and the on-chip
debug security IDs to 0085H to 008EH and 1085H to 108EH.
2. Writing boot cluster 0 can be prohibited depending on the setting of security (refer to 25.6 Security Settings).
Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers, refer
to Table 3-2 Correspondence Between Address Values and Block Numbers in Flash Memory.
Block 00H
Block 01H
Block 07H
1 KB
1FFFH
07FFH
0800H
0000H
0400H
03FFH
1C00H
1BFFH