Datasheet

78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA
R01UH0010EJ0500 Rev.5.00 545
Feb 28, 2012
Figure 15-33. Example of Master to Slave Communication
(When 9-Clock Wait Is Selected for Both Master and Slave) (3/3)
(3) Stop condition
IICA
ACKD0
STD0
SPD0
WTIM0
H
H
L
L
L
L
H
H
L
ACKE0
MSTS0
STT0
SPT0
WREL0
INTIICA0
TRC0
IICA
ACKD0
STD0
SPD0
WTIM0
ACKE0
MSTS0
STT0
SPT0
WREL0
INTIICA0
TRC0
SCLA0
SDAA0
123456789 21
D7 D6 D5 D4 D3 D2 D1 D0 AD5AD6
ACK
Processing by master device
Transfer lines
Processing by slave device
IICA ← data Note 1 IICA ← address
IICA ← FFH Note 2 IICA ← FFH Note 2
Stop
condition
Start
condition
Transmit
Note 2
Note 2
(When SPIE0 = 1)
Receive
(When SPIE0 = 1)
Notes 1. Write data to IICA, not setting WREL0, in order to cancel a wait state during master transmission.
2. To cancel slave wait, write “FFH” to IICA or set WREL0.