Datasheet

78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA
R01UH0010EJ0500 Rev.5.00 543
Feb 28, 2012
Figure 15-33. Example of Master to Slave Communication
(When 9-Clock Wait Is Selected for Both Master and Slave) (1/3)
(1) Start condition ~ address
IICA
ACKD0
STD0
SPD0
WTIM0
H
H
L
L
L
L
H
H
L
L
ACKE0
MSTS0
STT0
SPT0
WREL0
INTIICA0
TRC0
IICA
ACKD0
STD0
SPD0
WTIM0
ACKE0
MSTS0
STT0
SPT0
WREL0
INTIICA0
TRC0
SCLA0
SDAA0
123456789 4321
AD6 AD5 AD4 AD3 AD2 AD1 AD0 W ACK D4D5D6D7
Note 2
Processing by master device
Transfer lines
Processing by slave device
IICA ← address IICA ← data Note 1
IICA ← FFH Note 2
Transmit
Start condition
Receive
Notes 1. Write data to IICA, not setting WREL0, in order to cancel a wait state during master transmission.
2. To cancel slave wait, write “FFH” to IICA or set WREL0.