Datasheet
78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA
R01UH0010EJ0500 Rev.5.00 517
Feb 28, 2012
Figure 15-30. Master Operation in Multi-Master System (3/3)
Writing IICA
WTIM0 = 1
WREL0 = 1
Reading IICA
ACKE0 = 1
WTIM0 = 0
WTIM0 = WREL0 = 1
ACKE0 = 0
Writing IICA
Yes
TRC0 = 1?
Restart?
MSTS0 = 1?
Starts communication
(specifies an address and transfer direction).
Starts transmission.
No
Yes
Waits for data reception.
Starts reception.
Yes
No
INTIICA0
interrupt occurs?
Yes
No
Transfer end?
Waits for detection of ACK.
Yes
No
INTIICA0
interrupt occurs?
Waits for data transmission.
Does not participate
in communication.
Yes
No
INTIICA0
interrupt occurs?
No
Yes
ACKD0 = 1?
No
Yes
No
C
2
Yes
MSTS0 = 1?
No
Yes
Transfer end?
No
Yes
ACKD0 = 1?
No
2
Yes
MSTS0 = 1?
No
2
Waits for detection of ACK.
Yes
No
INTIICA0
interrupt occurs?
Yes
MSTS0 = 1?
No
C
2
Yes
EXC0 = 1 or COI0 = 1?
No
1
2
SPT0 = 1
STT0 = 1
Slave operation
END
Communication processingCommunication processing
Remarks 1. Conform to the specifications of the product that is communicating, with respect to the transmission and
reception formats.
2. To use the device as a master in a multi-master system, read the MSTS0 bit each time interrupt INTIICA0
has occurred to check the arbitration result.
3. To use the device as a slave in a multi-master system, check the status by using the IICAS0 and IICAF0
registers each time interrupt INTIICA0 has occurred, and determine the processing to be performed next.