Datasheet

78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA
R01UH0010EJ0500 Rev.5.00 509
Feb 28, 2012
Figure 15-26 shows the communication reservation timing.
Figure 15-26. Communication Reservation Timing
21 3456 21 3456789
SCLA0
SDAA0
Program processing
Hardware processing
Write to
IICA
Set SPD0
and
INTIICA0
STT0 = 1
Communi-
cation
reservation
Set
STD0
Generate by master device with bus mastership
Remark IICA: IICA shift register
STT0: Bit 1 of IICA control register 0 (IICACTL0)
STD0: Bit 1 of IICA status register 0 (IICAS0)
SPD0: Bit 0 of IICA status register 0 (IICAS0)
Communication reservations are accepted via the timing shown in Figure 15-27. After bit 1 (STD0) of the IICA
status register 0 (IICAS0) is set to 1, a communication reservation can be made by setting bit 1 (STT0) of the IICA
control register 0 (IICACTL0) to 1 before a stop condition is detected.
Figure 15-27. Timing for Accepting Communication Reservations
SCLA0
SDAA0
STD0
SPD0
Standby mode (Communication can be reserved by setting STT0 to 1 during this period.)
Figure 15-28 shows the communication reservation protocol.