Datasheet
78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA
R01UH0010EJ0500 Rev.5.00 500
Feb 28, 2012
15.5.7 Canceling wait
The I
2
C usually cancels a wait state by the following processing.
Writing data to IICA shift register (IICA)
Setting bit 5 (WREL0) of IICA control register 0 (IICACTL0) (canceling wait)
Setting bit 1 (STT0) of IICACTL0 register (generating start condition)
Note
Setting bit 0 (SPT0) of IICACTL0 register (generating stop condition)
Note
Note Master only
When the above wait canceling processing is executed, the I
2
C cancels the wait state and communication is resumed.
To cancel a wait state and transmit data (including addresses), write the data to the IICA register.
To receive data after canceling a wait state, or to complete data transmission, set bit 5 (WREL0) of the IICA control
register 0 (IICACTL0) to 1.
To generate a restart condition after canceling a wait state, set bit 1 (STT0) of the IICACTL0 register to 1.
To generate a stop condition after canceling a wait state, set bit 0 (SPT0) of the IICACTL0 register to 1.
Execute the canceling processing only once for one wait state.
If, for example, data is written to the IICA register after canceling a wait state by setting the WREL0 bit to 1, an incorrect
value may be output to SDAA0 line because the timing for changing the SDAA0 line conflicts with the timing for writing the
IICA register.
In addition to the above, communication is stopped if the IICE0 bit is cleared to 0 when communication has been
aborted, so that the wait state can be canceled.
If the I
2
C bus has deadlocked due to noise, processing is saved from communication by setting bit 6 (LREL0) of the
IICACTL0 register, so that the wait state can be canceled.
Caution If a processing to cancel a wait state executed when WUP (bit 7 of the IICA control register 1
(IICACTL1)) = 1, the wait state will not be canceled.