Datasheet

78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA
R01UH0010EJ0500 Rev.5.00 499
Feb 28, 2012
Figure 15-21. Wait (2/2)
(2) When master and slave devices both have a nine-clock wait
(master transmits, slave receives, and ACKE0 = 1)
Master
IICA
SCLA0
Slave
IICA
SCLA0
ACKE0
Transfer lines
SCLA0
SDAA0
H
6789 1 23
Master and slave both wait
after output of ninth clock
Wait from
master and
slave
Wait from slave
IICA data write (cancel wait)
FFH is written to IICA or WREL0 is set to 1
6789 123
D2 D1 D0 ACK D7 D6 D5
Generate according to previously set ACKE0 value
Remark ACKE0: Bit 2 of IICA control register 0 (IICACTL0)
WREL0: Bit 5 of IICA control register 0 (IICACTL0)
A wait may be automatically generated depending on the setting of bit 3 (WTIM0) of the IICA control register 0
(IICACTL0).
Normally, the receiving side cancels the wait state when bit 5 (WREL0) of the IICACTL0 register is set to 1 or when
FFH is written to the IICA shift register (IICA), and the transmitting side cancels the wait state when data is written to the
IICA register.
The master device can also cancel the wait state via either of the following methods.
• By setting bit 1 (STT0) of IICACTL0 register to 1
• By setting bit 0 (SPT0) of IICACTL0 register to 1