Datasheet
78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA
R01UH0010EJ0500 Rev.5.00 491
Feb 28, 2012
(8) Port output mode register 6 (POM6)
This register sets the output mode of P60 and P61 in 1-bit units. During I
2
C communication, set POM60 and POM61
to 1.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 15-12. Format of Port Output Mode Register 6 (POM6)
Address: FF2AH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
POM6 0 0 0 0 0 0 POM61 POM60
POM6n P6n pin output mode selection (n = 0, 1)
0 Normal output (CMOS output) mode
1 N-ch open drain output (VDD tolerance) mode
(9) Port mode register 6 (PM6)
This register sets the input/output of port 6 in 1-bit units.
When using the P60/SCLA0/TxD6 pin as clock I/O and the P61/SDAA0/RxD6 pin as serial data I/O, clear PM60
and PM61 to 0, and set the output latches of P60 and P61 to 1.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
Figure 15-13. Format of Port Mode Register 6 (PM6)
PM60PM61111111
P6n pin I/O mode selection (n = 0, 1)
Output mode (output buffer on)
Input mode (output buffer off)
PM6n
0
1
01234567
PM6
Address: FF26H After reset: FFH R/W
Symbol