Datasheet

78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA
R01UH0010EJ0500 Rev.5.00 490
Feb 28, 2012
(5) IICA low-level width setting register (IICWL)
This register is used to set the low-level width of the SCLA0 pin signal that is output by serial interface IICA being in
master mode.
This register can be set by an 8-bit memory manipulation instruction.
Set this register while operation of I
2
C is disabled (bit 7 (IICE0) of the IICA control register 0 (IICACTL0) is 0).
Reset signal generation sets this register to FFH.
Figure 15-9. Format of IICA Low-Level Width Setting Register (IICWL)
Address: FFADH After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
IICWL
(6) IICA high-level width setting register (IICWH)
This register is used to set the high-level width of the SCLA0 pin signal that is output by serial interface IICA being
in master mode.
This register can be set by an 8-bit memory manipulation instruction.
Set this register while operation of I
2
C is disabled (bit 7 (IICE0) of the IICA control register 0 (IICACTL0) is 0).
Reset signal generation sets this register to FFH.
Figure 15-10. Format of IICA High-Level Width Setting Register (IICWH)
Address: FFAEH After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
IICWH
Remark For how to set the transfer clock by using the IICWL and IICWH registers, see 15.4.2 Setting transfer
clock by using IICWL and IICWH registers.
(7) Port input mode register 6 (PIM6)
This register sets the input buffer of P60 and P61 in 1-bit units. When using an input compliant with the SMBus
specifications in I
2
C communication, set PIM60 and PIM61 to 1.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 15-11. Format of Port Input Mode Register 6 (PIM6)
Address: FF3EH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
PIM6 0 0 0 0 0 0 PIM61 PIM60
PIM6n P6n pin input buffer selection (n = 0, 1)
0 Normal input (Schmitt) buffer
1 SMBus input buffer