Datasheet

78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA
R01UH0010EJ0500 Rev.5.00 489
Feb 28, 2012
Figure 15-8. Format of IICA Control Register 1 (IICACTL1) (2/2)
CLD0 Detection of SCLA0 pin level (valid only when IICE0 = 1)
0 The SCLA0 pin was detected at low level.
1 The SCLA0 pin was detected at high level.
Condition for clearing (CLD0 = 0) Condition for setting (CLD0 = 1)
 When the SCLA0 pin is at low level
 When IICE0 = 0 (operation stop)
 Reset
 When the SCLA0 pin is at high level
DAD0 Detection of SDAA0 pin level (valid only when IICE0 = 1)
0 The SDAA0 pin was detected at low level.
1 The SDAA0 pin was detected at high level.
Condition for clearing (DAD0 = 0) Condition for setting (DAD0 = 1)
 When the SDAA0 pin is at low level
 When IICE0 = 0 (operation stop)
 Reset
 When the SDAA0 pin is at high level
SMC0 Operation mode switching
0 Operates in standard mode.
1 Operates in fast mode.
DFC0 Digital filter operation control
0 Digital filter off.
1 Digital filter on.
Digital filter can be used only in fast mode.
In fast mode, the transfer clock does not vary, regardless of the DFC0 bit being set (1) or cleared (0).
The digital filter is used for noise elimination in fast mode.
Remark IICE0: Bit 7 of IICA control register 0 (IICACTL0)