Datasheet
78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA
R01UH0010EJ0500 Rev.5.00 488
Feb 28, 2012
(4) IICA control register 1 (IICACTL1)
This register is used to set the operation mode of I
2
C and detect the statuses of the SCLA0 and SDAA0 pins.
This register can be set by a 1-bit or 8-bit memory manipulation instruction. However, the CLD0 and DAD0 bits are
read-only.
Set the IICACTL1 register, except the WUP bit, while operation of I
2
C is disabled (bit 7 (IICE0) of IICA control
register 0 (IICACTL0) is 0).
Reset signal generation clears this register to 00H.
Figure 15-8. Format of IICA Control Register 1 (IICACTL1) (1/2)
Address: FFA8H After reset: 00H R/W
Note 1
Symbol 7 6 <5> <4> <3> <2> 1 0
IICACTL1 WUP 0 CLD0 DAD0 SMC0 DFC0 0 0
WUP Control of address match wakeup
0 Stops operation of address match wakeup function in STOP mode.
1 Enables operation of address match wakeup function in STOP mode.
To shift to STOP mode when WUP = 1, execute the STOP instruction at least three clocks after setting (1) WUP
bit (see Figure 15-23 Flow When Setting WUP = 1).
Clear (0) the WUP bit after the address has matched or an extension code has been received. The subsequent
communication can be entered by clearing (0) the WUP bit (The wait must be released and transmit data must
be written after the WUP bit has been cleared (0).).
The interrupt timing when the address has matched or when an extension code has been received, while WUP
= 1, is identical to the interrupt timing when WUP = 0. (A delay of the difference of sampling by the clock will
occur.) Furthermore, when WUP = 1, a stop condition interrupt is not generated even if the SPIE0 bit is set to 1.
Condition for clearing (WUP = 0) Condition for setting (WUP = 1)
Cleared by instruction (after address match or
extension code reception)
Set by instruction (when MSTS0, EXC0, and COI0
are “0”, and STD0 also “0” (communication not
entered))
Note 2
Notes 1. Bits 4 and 5 are read-only.
2. The status of IICAS0 must be checked and WUP must be set during the period shown below.
SCLA0
<1> <2>
SDAA0
A6 A5 A4 A3 A2 A1 A0
The maximum time from reading IICAS0 to setting
WUP is the period from <1> to <2>.
Check the IICAS0 operation status and set
WUP during this period.
R/W