Datasheet

78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA
R01UH0010EJ0500 Rev.5.00 484
Feb 28, 2012
(2) IICA status register 0 (IICAS0)
This register indicates the status of I
2
C.
This register is read by a 1-bit or 8-bit memory manipulation instruction only when STT0 = 1 and during the wait
period.
Reset signal generation clears this register to 00H.
Caution Reading the IICAS0 register while the address match wakeup function is enabled (WUP = 1) in
STOP mode is prohibited. When the WUP bit is changed from 1 to 0 (wakeup operation is
stopped), regardless of the INTIICA0 interrupt request, the change in status is not reflected until
the next start condition or stop condition is detected. To use the wakeup function, therefore,
enable (SPIE0 = 1) the interrupt generated by detecting a stop condition and read the IICAS0
register after the interrupt has been detected.
Remark STT0: Bit 1 of IICA control register 0 (IICACTL0)
WUP: Bit 7 of IICA control register 1 (IICACTL1)
Figure 15-6. Format of IICA Status Register 0 (IICAS0) (1/3)
Address: FFAAH After reset: 00H R
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
IICAS0 MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0
MSTS0 Master status
0 Slave device status or communication standby status
1 Master device communication status
Condition for clearing (MSTS0 = 0) Condition for setting (MSTS0 = 1)
 When a stop condition is detected
 When ALD0 = 1 (arbitration loss)
 Cleared by LREL0 = 1 (exit from communications)
 When the IICE0 bit changes from 1 to 0 (operation
stop)
 Reset
 When a start condition is generated
ALD0 Detection of arbitration loss
0 This status means either that there was no arbitration or that the arbitration result was a “win”.
1 This status indicates the arbitration result was a “loss”. The MSTS0 bit is cleared.
Condition for clearing (ALD0 = 0) Condition for setting (ALD0 = 1)
 Automatically cleared after the IICAS0 register is
read
Note
 When the IICE0 bit changes from 1 to 0 (operation
stop)
 Reset
 When the arbitration result is a “loss”.
Note This register is also cleared when a 1-bit memory manipulation instruction is executed for bits other
than the ALD0 bit of the IICAS0 register. Therefore, when using the ALD0 bit, read the data of this
bit before the data of the other bits.
Remark LREL0: Bit 6 of IICA control register 0 (IICACTL0)
IICE0: Bit 7 of IICA control register 0 (IICACTL0)