Datasheet

78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA
R01UH0010EJ0500 Rev.5.00 480
Feb 28, 2012
Figure 15-5. Format of IICA Control Register 0 (IICACTL0) (1/4)
Address: FFA7H After reset: 00H R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
IICACTL0 IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0
IICE0 I
2
C operation enable
0 Stop operation. Reset the IICA status register 0 (IICAS0)
Note 1
. Stop internal operation.
1 Enable operation.
Be sure to set this bit (1) while the SCLA0 and SDLA0 lines are at high level.
Condition for clearing (IICE0 = 0) Condition for setting (IICE0 = 1)
 Cleared by instruction
 Reset
 Set by instruction
LREL0
Note s 2,
3
Exit from communications
0 Normal operation
1 This exits from the current communications and sets standby mode. This setting is automatically cleared
to 0 after being executed.
Its uses include cases in which a locally irrelevant extension code has been received.
The SCLA0 and SDAA0 lines are set to high impedance.
The following flags of IICA control register 0 (IICACTL0) and IICA status register 0 (IICAS0) are cleared
to 0.
• STT0 • SPT0 • MSTS0 • EXC0 • COI0 • TRC0 • ACKD0 • STD0
The standby mode following exit from communications remains in effect until the following communications entry
conditions are met.
 After a stop condition is detected, restart is in master mode.
 An address match or extension code reception occurs after the start condition.
Condition for clearing (LREL0 = 0) Condition for setting (LREL0 = 1)
 Automatically cleared after execution
 Reset
 Set by instruction
WREL0
Note s
2, 3
Wait cancellation
0 Do not cancel wait
1 Cancel wait. This setting is automatically cleared after wait is canceled.
When WREL0 is set (wait canceled) during the wait period at the ninth clock pulse in the transmission status (TRC0 =
1), the SDAA0 line goes into the high impedance state (TRC0 = 0).
Condition for clearing (WREL0 = 0) Condition for setting (WREL0 = 1)
 Automatically cleared after execution
 Reset
 Set by instruction
Notes 1. The IICAS0 register, the STCF and IICBSY bits of the IICAF0 register, and the CLD0 and DAD0
bits of the IICACTL1 register are reset.
2. The signals of these bits are invalid while the IICE0 bit is 0.
3. When the LREL0 and WREL0 bits are read, 0 is always read.
Caution If the operation of I
2
C is enabled (IICE0 = 1) when the SCLA0 line is high level, the SDAA0
line is low level, and the digital filter is turned on (DFC0 of the IICACTL1 register = 1), a start
condition will be inadvertently detected immediately. In this case, set (1) the LREL0 bit by
using a 1-bit memory manipulation instruction immediately after enabling operation of I
2
C
(IICE0 = 1).