Datasheet

78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA

R01UH0010EJ0500 Rev.5.00 479

Feb 28, 2012

(13) Bus status detector

This circuit detects whether or not the bus is released by detecting start conditions and stop conditions.

However, as the bus status cannot be detected immediately following operation, the initial status is set by the

STCEN bit.

Remark STT0 bit: Bit 1 of IICA control register 0 (IICACTL0)

SPT0 bit: Bit 0 of IICA control register 0 (IICACTL0)

IICRSV bit: Bit 0 of IICA flag register 0 (IICAF0)

IICBSY bit: Bit 6 of IICA flag register 0 (IICAF0)

STCF bit: Bit 7 of IICA flag register 0 (IICAF0)

STCEN bit: Bit 1 of IICA flag register 0 (IICAF0)

15.3 Registers Controlling Serial Interface IICA

Serial interface IICA is controlled by the following ten registers.

• IICA control register 0 (IICACTL0)

• IICA status register 0 (IICAS0)

• IICA flag register (IICAF0)

• IICA control register 1 (IICACTL1)

• IICA low-level width setting register (IICWL)

• IICA high-level width setting register (IICWH)

• Port input mode register 6 (PIM6)

• Port output mode register 6 (POM6)

• Port mode register 6 (PM6)

• Port register 6 (P6)

(1) IICA control register 0 (IICACTL0)

This register is used to enable/stop I

C operations, set wait timing, and set other I

C operations.

This register can be set by a 1-bit or 8-bit memory manipulation instruction. However, set the SPIE0, WTIM0, and

ACKE0 bits while IICE0 = 0 or during the wait period. These bits can be set at the same time when the IICE0 bit is

set from “0” to “1”.

Reset signal generation clears this register to 00H.