Datasheet

78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA
R01UH0010EJ0500 Rev.5.00 477
Feb 28, 2012
15.2 Configuration of Serial Interface IICA
Serial interface IICA includes the following hardware.
Table 15-1. Configuration of Serial Interface IICA
Item Configuration
Registers
IICA shift register (IICA)
Slave address register 0 (SVA0)
Control registers
IICA control register 0 (IICACTL0)
IICA status register 0 (IICAS0)
IICA flag register 0 (IICAF0)
IICA control register 1 (IICACTL1)
IICA low-level width setting register (IICWL)
IICA high-level width setting register (IICWH)
Port input mode register 6 (PIM6)
Port output mode register 6 (POM6)
Port mode register 6 (PM6)
Port register 6 (P6)
(1) IICA shift register (IICA)
This register is used to convert 8-bit serial data to 8-bit parallel data and vice versa in synchronization with the
serial clock. This register can be used for both transmission and reception.
The actual transmit and receive operations can be controlled by writing and reading operations to this register.
Cancel the wait state and start data transfer by writing data to this register during the wait period.
This register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears IICA to 00H.
Figure 15-3. Format of IICA Shift Register (IICA)
Symbol
IICA
Address: FFA5H After reset: 00H R/W
76543210
Cautions 1. Do not write data to the IICA register during data transfer.
2. Write or read the IICA register only during the wait period. Accessing the IICA register in a
communication state other than during the wait period is prohibited. When the device serves
as the master, however, the IICA register can be written only once after the communication
trigger bit (STT0) is set to 1.
3. When communication is reserved, write data to the IICA register after the interrupt triggered
by a stop condition is detected.
(2) Slave address register 0 (SVA0)
This register stores seven bits of local addresses {A6, A5, A4, A3, A2, A1, A0} when in slave mode.
This register can be set by an 8-bit memory manipulation instruction.
However, rewriting to this register is prohibited while STD0 = 1 (while the start condition is detected).
Reset signal generation clears SVA0 to 00H.