Datasheet

78K0/Ix2 CHAPTER 15 SERIAL INTERFACE IICA
R01UH0010EJ0500 Rev.5.00 475
Feb 28, 2012
Figure 15-1. Block Diagram of Serial Interface IICA
IICE0
DQ
DFC0
SDAA0/P61/
RxD6
SCLA0/P60/
TxD6
INTIICA0
IICACTL0.STT0, SPT0
IICAS0.MSTS0, EXC0, COI0
IICAS0.MSTS0,
EXC0, COI0
LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0
MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0
STCF IICBSY STCEN IICRSV
WUP CLD0 DAD0 DFC0SMC0
PM60
Internal bus
IICA status register 0 (IICAS0)
IICA control register 0
(IICACTL0)
Slave address
register 0 (SVA0)
Noise
eliminator
Match
signal
Match signal
IICA shift
register (IICA)
SO latch
Set
Clear
IICWL
TRC0
DFC0
Data hold
time correction
circuit
Start
condition
generator
Stop
condition
generator
ACK
generator
Wakeup
controller
N-ch open-
drain output
PM61
Noise
eliminator
Bus status
detector
ACK detector
Stop condition
detector
Serial clock
counter
Interrupt request
signal generator
Serial clock
controller
Serial clock
wait controller
Start condition
detector
Internal bus
IICA flag register 0
(IICAF0)
IICA control register 1
(IICACTL1)
N-ch open-
drain output
Output
latch
(P60)
Output
latch
(P61)
WUP
Sub-circuit
for standby
Filter
Filter
Output control
IICA shift register (IICA)
Counter
IICA low-level width
setting register (IICWL)
IICA high-level width
setting register (IICWH)
fCLK
POM61
POM60