Datasheet

78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI
R01UH0010EJ0500 Rev.5.00 471
Feb 28, 2012
(4) Permissible baud rate range during reception (UART mode)
The permissible error from the baud rate at the transmission destination during reception in UART mode is shown
below.
Cautions 1. Make sure that the baud rate error during reception in UART mode is within the permissible error
range, by using the calculation expression shown below.
2. The allowable error ranges are “baud rate error  25%” and “duty error  12.5%” during reception
in DALI mode. Be sure to use the baud rate and duty within the allowable error ranges.
Figure 14-35. Permissible Baud Rate Range During Reception
FL
1 data frame (11 × FL)
FLmin
FLmax
Data frame length
of UART6
Start bit
Bit 0 Bit 1 Bit 7
Parity bit
Minimum permissible
data frame length
Maximum permissible
data frame length
Stop bit
Start bit
Bit 0 Bit 1 Bit 7
Parity bit
Latch timing
Stop bit
Start bit
Bit 0 Bit 1 Bit 7
Parity bit Stop bit
As shown in Figure 14-35, the latch timing of the receive data is determined by the counter set by baud rate generator
control register 6 (BRGC6) after the start bit has been detected. If the last data (stop bit) meets this latch timing, the
data can be correctly received.
Assuming that 11-bit data is received, the theoretical values can be calculated as follows.
FL = (Brate)

1
Brate: Baud rate of UART6
k: Set value of BRGC6
FL: 1-bit data length
Margin of latch timing: 2 clocks