Datasheet

78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI
R01UH0010EJ0500 Rev.5.00 462
Feb 28, 2012
(3) Registers used
 UART/DALI mode control register (UADLCTL)
 UART/DALI operation mode register 6 (ASIM6)
 UART/DALI reception error status register 6 (ASIS6)
 Clock selection register 6 (CKSR6)
 Baud rate generator control register 6 (BRGC6)
 Port mode register 6 (PM6)
 Port register 6 (P6)
 Port output mode register 6 (POM6)
The basic procedure of setting an operation in the DALI mode is as follows.
<1> Set bit 0 (UADLCTL) of UADLCTL register to 1 (refer to Figure 14-5).
<2> Set the CKSR6 register (refer to Figure 14-9).
<3> Set the BRGC6 register (refer to Figure 14-10).
<4> Set bit 0 (ISRM6) of the ASIM6 register (refer to Figure 14-6).
<5> Set bit 7 (POWER6) of the ASIM6 register to 1.
<6> Set bit 5 (RXE6) of the ASIM6 register to 1.  Reception is enabled.
Caution Take relationship with the other party of communication when setting the port mode register and
port register.
The relationship between the register settings and pins is shown below.
Table 14-4. Relationship Between Register Settings and Pins
Pin Function POWER
6
TXE6 RXE6 PM60 P60 PM61 P61 POM60 POM61 DALI
Operation
T
XD6/
SCLA0/
P60
RXD6/
SDAA0/
P61

Note

Note

Note

Note

Note

Note
P60 P61 0 0 0
0 1 0 1 1 1
Stop
SCLA0 SDAA0
0 1

Note

Note
1


Note

Reception P60 R
XD6
1 0 0 1

Note

Note
0

Note
Transmission TXD6 P61
1
1 1 0 1 1

0

Transmission/
reception
T
XD6 RXD6
Note Can be set as port function.
Remark : don’t care
POWER6: Bit 7 of UART/DALI operation mode register 6 (ASIM6)
TXE6: Bit 6 of ASIM6
RXE6: Bit 5 of ASIM6
PM6: Port mode register
P6: Port output latch
POM60, POM61: Bits 0 and 1 of Port output mode register 6 (POM6)