Datasheet

78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI
R01UH0010EJ0500 Rev.5.00 456
Feb 28, 2012
(e) Normal reception
Reception is enabled and the R
XD6 pin input is sampled when bit 7 (POWER6) of UART/DALI operation mode
register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1.
The 8-bit counter of the baud rate generator starts counting when the falling edge of the R
XD6 pin input is
detected. When the set value of baud rate generator control register 6 (BRGC6) has been counted, the RXD6 pin
input is sampled again ( in Figure 14-21). If the R
XD6 pin is low level at this time, it is recognized as a start bit.
When the start bit is detected, reception is started, and serial data is sequentially stored in the UART/DALI
receive shift register (RXS6) at the set baud rate. When the stop bit has been received, the reception completion
interrupt (INTSR6) is generated and the data of RXS6 is written to UART receive buffer register 6 (RXB6). If an
overrun error (OVE6) occurs, however, the receive data is not written to RXB6.
Even if a parity error (PE6) occurs while reception is in progress, reception continues to the reception position of
the stop bit, and a reception error interrupt (INTSR6/INTSRE6) is generated on completion of reception.
Figure 14-21. Reception Completion Interrupt Request Timing
RXD6 (input)
INTSR6
Start D0 D1 D2 D3 D4 D5 D6 D7 Parity
RXB6
Stop
Cautions 1. If a reception error occurs, read ASIS6 and then RXB6 to clear the error flag. Otherwise, an
overrun error will occur when the next data is received, and the reception error status will
persist.
2. Reception is always performed with the “number of stop bits = 1”. The second stop bit is
ignored.
3. Be sure to read UART/DALI reception error status register 6 (ASIS6) before reading RXB6.