Datasheet

78K0/Ix2 CHAPTER 2 PIN FUNCTIONS

R01UH0010EJ0500 Rev.5.00 33

Feb 28, 2012

(1) Port mode

P121, P122, and P125 function as an input port. Only for P125, use of an on-chip pull-up resistor can be specified by

pull-up resistor option register 12 (PU12).

(2) Control mode

P121, P122, and P125 function as pins for external interrupt request input, connecting resonator for main system

clock, external clock input for main system clock, external reset input, timer input, and clock input and data I/O for

flash memory programmer/on-chip debugger.

(a) INTP0

This functions as an external interrupt request input (INTP0) for which the valid edge (rising edge, falling edge, or

both rising and falling edges) can be specified.

(b) X1, X2

These are pins for connecting a resonator for main system clock.

This is an external clock input pin for main system clock.

(d) RESET

This is the active-low system reset input pin.

(e) TI000

This is a pin for inputting an external count clock to 16-bit timer/event counter 00 and is also for inputting a

capture trigger signal to the capture registers (CR000, CR010) of 16-bit timer/event counter 00.

(f) TOOLC0

This is a clock input pin for flash memory programmer/on-chip debugger.

(g) TOOLD0

This is a data I/O pin for flash memory programmer/on-chip debugger.

Caution Because RESET/P125 immediately after release of reset is set in the external reset input, if a reset

signal is generated during low level input, the reset status continues until the input rises to the high

level.

Remark For how to connect a flash memory programmer using TOOLC0/X1, TOOLD0/X2, refer to CHAPTER 25

FLASH MEMORY. For how to connect TOOLC0/X1, TOOLD0/X2 and an on-chip debug emulator, refer to

CHAPTER 26 ON-CHIP DEBUG FUNCTION.

2.2.7 AV

REF, AVSS, VDD, VSS

78K0/IY2 78K0/IA2 78K0/IB2

16 Pins 20 Pins 30 Pins/32 Pins

AVREF AVREF AVREF

 

VDD VDD VDD

VSS VSS VSS