Datasheet
78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI
R01UH0010EJ0500 Rev.5.00 440
Feb 28, 2012
(6) Baud rate generator control register 6 (BRGC6)
This register sets the division value of the 8-bit counter of serial interface UART6/DALI.
BRGC6 can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
Remark BRGC6 can be refreshed (the same value is written) by software during a communication operation
(when bits 7 and 6 (POWER6, TXE6) of ASIM6 = 1 or bits 7 and 5 (POWER6, RXE6) of ASIM6 = 1).
Figure 14-10. Format of Baud Rate Generator Control Register 6 (BRGC6)
Address: FF57H After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
BRGC6 MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60
Output clock selection of
8-bit counter
MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60 k
UART mode DALI mode
0 0 0 0 0 0
Setting
prohibited
0 0 0 0 0 1 0 0 4 fXCLK6/4
0 0 0 0 0 1 0 1 5 fXCLK6/5
0 0 0 0 0 1 1 0 6 fXCLK6/6
0 0 0 0 0 1 1 1 7 fXCLK6/7
Setting
prohibited
0 0 0 0 1 0 0 0 8 fXCLK6/8
1 1 1 1 1 1 0 0 252 fXCLK6/252
1 1 1 1 1 1 0 1 253 fXCLK6/253
1 1 1 1 1 1 1 0 254 fXCLK6/254
1 1 1 1 1 1 1 1 255 fXCLK6/255
Cautions 1. Make sure that bit 6 (TXE6) and bit 5 (RXE6) of the ASIM6 register = 0 when rewriting the MDL67
to MDL60 bits.
2. In UART mode the baud rate is the output clock of the 8-bit counter divided by 2.
3. In DALI mode the baud rate is the output clock of the 8-bit counter divided by 4.
Remarks 1. f
XCLK6: Frequency of base clock selected by the TPS63 to TPS60 bits of CKSR6 register
2. k: Value set by MDL67 to MDL60 bits (k = 4, 5, 6, ..., 255)
3. : Don’t care