Datasheet

78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI
R01UH0010EJ0500 Rev.5.00 439
Feb 28, 2012
Figure 14-9. Format of Clock Selection Register 6 (CKSR6)
Address: FF56H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
CKSR6 0 0 0 0 TPS63 TPS62 TPS61 TPS60
Base clock (fXCLK6) selection TPS63 TPS62 TPS61 TPS60
f
PRS =
2 MHz
fPRS =
5 MHz
fPRS =
10 MHz
fPRS =
20 MHz
(when
using PLL)
0 0 0 0 fPRS 2 MHz 5 MHz 10 MHz 20 MHz
0 0 0 1 fPRS/2 1 MHz 2.5 MHz 5 MHz 10 MHz
0 0 1 0 fPRS/2
2
500 kHz 1.25 MHz 2.5 MHz 5 MHz
0 0 1 1 fPRS/2
3
250 kHz 625 kHz 1.25 MHz 2.5 MHz
0 1 0 0 fPRS/2
4
125 kHz 312.5 kHz 625 kHz 1.25 MHz
0 1 0 1 fPRS/2
5
62.5 kHz 156.25 kHz 312.5 kHz 625 kHz
0 1 1 0 fPRS/2
6
31.25 kHz 78.13 kHz 156.25 kHz 312.5 kHz
0 1 1 1 fPRS/2
7
15.625 kHz 39.06 kHz 78.13 kHz 156.25 kHz
1 0 0 0 fPRS/2
8
7.813 kHz 19.53 kHz 39.06 kHz 78.13 kHz
1 0 0 1 fPRS/2
9
3.906 kHz 9.77 kHz 19.53 kHz 39.06 kHz
1 0 1 0
f
PRS/2
1
0
1.953 kHz 4.88 kHz 9.77 kHz 19.53 kHz
Other than above Setting prohibited
Caution Make sure POWER6 = 0 when rewriting TPS63 to TPS60.
Remarks 1. f
PRS: Peripheral hardware clock frequency
2. TMC506: Bit 6 of 8-bit timer mode control register 50 (TMC50)
TMC501: Bit 1 of TMC50