Datasheet

78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI
R01UH0010EJ0500 Rev.5.00 437
Feb 28, 2012
(3) UART/DALI reception error status register 6 (ASIS6)
This register indicates an error status on completion of reception by serial interface UART6/DALI. This register is
read-only by an 8-bit memory manipulation instruction.
Reset signal generation, or clearing bit 7 (POWER6) or bit 5 (RXE6) of ASIM6 to 0 clears this register to 00H. 00H is
read when this register is read.
If a reception error occurs, read ASIS6 and then read UART receive buffer register (RXB6) or DALI receive buffer
register (RXBDL) to clear the error flag.
Cautions 1. Only the PE6, FE6, and OVE6 bits are used in UART mode (UADLSEL = 0). The read value of the
MFE bit is 0 in UART mode.
2. Only the MFE, FE6, and OVE6 bits are used in DALI mode (UADLSEL = 1). The read value of the
PE6 bit is 0 in DALI mode.
Figure 14-7. Format of UART/DALI Reception Error Status Register 6 (ASIS6)
Address: FF53H After reset: 00H R
Symbol 7 6 5 4 3 2 1 0
ASIS6 MFE 0 0 0 0 PE6 FE6 OVE6
MFE Status flag indicating Manchester framing error
0 If POWER6 = 0 or RXE6 = 0, or if ASIS6 register is read
1 When undecodable data is detected during DALI reception
PE6 Status flag indicating parity error
0 If POWER6 = 0 or RXE6 = 0, or if ASIS6 register is read
1 If the parity of transmit data does not match the parity bit on completion of UART reception
FE6 Status flag indicating framing error
0 If POWER6 = 0 or RXE6 = 0, or if ASIS6 register is read
1 If the stop bit is not detected on completion of UART or DALI reception
OVE6 Status flag indicating overrun error
0 If POWER6 = 0 or RXE6 = 0, or if ASIS6 register is read
1
If receive data is set to the RXB6 register and the next reception operation is completed before the
data is read.
Cautions 1. The operation of the PE6 bit differs depending on the set values of the PS61 and PS60 bits of
UART/DALI operation mode register 6 (ASIM6).
2. For the stop bit of the receive data, only the first stop bit is checked regardless of the number of
stop bits.
3. If an overrun error occurs, the next receive data is not written to UART receive buffer register 6
(RXB6) or DALI receive buffer register (RXBDL) but discarded.
4. If data is read from ASIS6, a wait cycle is generated. Do not read data from ASIS6 when the
peripheral hardware clock (f
PRS) is stopped. For details, refer to CHAPTER 31 CAUTIONS FOR
WAIT.