Datasheet

78K0/Ix2 CHAPTER 14 SERIAL INTERFACE UART6/DALI
R01UH0010EJ0500 Rev.5.00 432
Feb 28, 2012
Figure 14-4. Block Diagram of Serial Interface UART6/DALI
Internal bus
UART/DALI
transmit
buffer register
6 (TXB6)
UART/DALI transmit
shift register
6 (TXS6)
INTST6
Baud rate
generator
LIN operation
control register 6 (ASICL6)
Reception control
UART/
DALI receive
shift register
6 (RXS6)
UART
receive
buffer register (
RXB6)
DALI receive
buffer register (RXBDL)
(2 bit)
TI000, INTP0
Note1
INTSR6
Baud rate
generator
Filter
INTSRE6
UART/DALI reception error
status registe 6 (ASIS6)
UART/DALI operation
mode register 6 (ASIM6)
UART transmission
status register 6 (ASIF6)
Transmission control
Registers
8
Reception unit Transmission unit
Clock selection
register6 (CKSR6)
Baud rate generator
control register
(BRGC6)
8
T
X
D6/
SCLA0/ P60
R
X
D6/SDAA0/P61
fPRS
fPRS/2
f
PRS/2
2
fPRS/2
3
fPRS/2
4
fPRS/2
5
fPRS/2
6
fPRS/2
7
fPRS/2
8
fPRS/2
9
fPRS/2
10
8-bit timer/
event counter
50 output
fXCLK6
Selector
Manchester
decoder
UART/DALI mode
control register (UADLCTL)
Manchester
encoder
LIN operation
control register 6 (ASICL6)
Output latch
(P60)
PM60
Selector
Selector
Note2
Notes 1. Selectable with input switch control register (ISC). 2. When using the P60/TxD6/SCLA0 pin as the data output of serial interface UART6/DALI, clear POM60 to 0