Datasheet

78K0/Ix2 CHAPTER 13 COMPARATORS
R01UH0010EJ0500 Rev.5.00 412
Feb 28, 2012
Figure 13-2. Format of Comparator 0 Control Register (C0CTL)
Address: FF62H After reset: 00H R/W
Symbol <7> <6> <5> <4> <3> 2 <1> <0>
C0CTL CMP0EN C0DFS1 C0DFS0 C0MODSEL1 C0MODSEL0 0 C0OE C0INV
CMP0EN Comparator 0 operation control
0 Stops operation
1 Enables operation
Enables input to the external pins (CMP0+) on the positive and negative sides of comparator 0
C0DFS1 C0DFS0 Noise elimination width setting
0 0 Noise filter unused
0 1 2/Fprs
1 0 2
2
/Fprs
1 1 2
4
/Fprs
C0MODSEL1 C0MODSEL0 Reference voltage selection
0 0 Internal reference voltage: DA0
0 1 Internal reference voltage: DA1
1 0 Internal reference voltage: DA2
1 1 Internal reference voltage: CMPCOM
Note
C0OE Enabling or disabling of comparator output
0 Disables output (output signal = fixed to low level)
1 Enables output
C0INV Output reversal setting
0 Forward
1 Reverse
Note Setting prohibited in the 78K0/IY1 and 78K0/IA2.
Cautions 1. Rewrite C0DFS1, C0DFS0, C0MODSEL1, C0MODSEL0, C0INV after setting the comparator 0
operation to the disabled state (CMP0EN = 0).
2. With the noise elimination width, an extra peripheral hardware clock frequency (f
PRS) may be
eliminated from the setting value.
3. If the comparator output noise interval is within “set noise elimination width + 1 clock”, an
illegal waveform may be output.
4. To use the internal reference voltage, enable (CVRE = 1) operation of the internal reference
voltage before enabling (CMP0EN = 1) the comparator operation.
Remark f
PRS: peripheral hardware clock frequency