Datasheet

78K0/Ix2 CHAPTER 12 OPERATIONAL AMPLIFIER
R01UH0010EJ0500 Rev.5.00 404
Feb 28, 2012
(3) Analog input channel specification register (ADS)
ADS specifies the input channel of the analog voltage to be A/D converted and sets the A/D conversion start method.
ADS can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears ADS to 00H.
Figure 12-4. Format of Analog Input Channel Specification Register (ADS)
(1) 78K0/IY2, 78K0/IA2
Address: FF0EH After reset: 00H R/W
Symbol <7> <6> <5> <4> 3 <2> <1> <0>
ADS V12SEL ADOAS ADTRG1 ADTRG0 0 ADS2 ADS1 ADS0
(2) 78K0/IB2
Address: FF0EH After reset: 00H R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
ADS V12SEL ADOAS ADTRG1 ADTRG0 ADS3 ADS2 ADS1 ADS0
ADS0ADS1ADS2ADS3 Analog input
channel
Input source
ANI0
ANI1
ANI2
Note 1
ANI3
ANI4
ANI5
ANI6
Note 2
ANI7
Note 2
ANI8
Note 2
PGA output
Note 3
Internal voltage (1.2 V)
P20/ANI0 pin
P21/ANI1 pin
P22/ANI2 pin
Note 1
P23/ANI3 pin
P24/ANI4 pin
P25/ANI5 pin
P26/ANI6 pin
Note 2
P27/ANI7 pin
Note 2
P70/ANI8 pin
Note 2
PGA output signal
Note 3
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
V12SEL
0
0
0
0
0
0
0
0
0
1
ADOAS
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Setting prohibitedOther than above
A/D conversion start method selection
Note 4
Normal start (software trigger mode)
TMX0 synchronization (timer trigger mode set by A/D conversion trigger signal of TMX0)
TMX1 synchronization (timer trigger mode set by A/D conversion trigger signal of TMX1)
Setting prohibited
ADTRG1
0
0
1
1
ADTRG0
0
1
0
1
Notes 1. Setting permitted in 78K0/IA2 and 78K0/IB2.
2. Setting permitted in 78K0/IB2.
3. Setting permitted in products with operational amplifier.
4. Switching the A/D conversion start method should be done after stopping the A/D conversion operation
(clearing (0) ADCS).