Datasheet

78K0/Ix2 CHAPTER 11 A/D CONVERTER
R01UH0010EJ0500 Rev.5.00 398
Feb 28, 2012
(7) AVREF pin input impedance
A series resistor string of several tens of k is connected between the AV
REF and AVSS pins.
Therefore, if the output impedance of the reference voltage source is high, this will result in a series connection to the
series resistor string between the AV
REF and AVSS pins, resulting in a large reference voltage error.
(8) Interrupt request flag (ADIF)
The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is
changed.
Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the pre-
change analog input may be set just before the ADS rewrite. Caution is therefore required since, at this time, when
ADIF is read immediately after the ADS rewrite, ADIF is set despite the fact A/D conversion for the post-change
analog input has not ended.
When A/D conversion is stopped and then resumed, clear ADIF before the A/D conversion operation is resumed.
Figure 11-26. Timing of A/D Conversion End Interrupt Request Generation
ADS rewrite
(start of ANIn conversion)
A
/D conversion
A
/D conversion
result register
ADIF
ANIn ANIn ANIm ANIm
ANIn ANIn ANIm ANIm
ADS rewrite
(start of ANIm conversion)
ADIF is set but ANIm conversion
has not ended.
Remarks 1. n = 0 to 8 (it depends on products)
2. m = 0 to 8 (it depends on products)
(9) Conversion results just after A/D conversion start
The first A/D conversion value immediately after A/D conversion starts may not fall within the rating range if the ADCS
bit is set to 1 within 1
 s after the ADCE bit was set to 1, or if the ADCS bit is set to 1 with the ADCE bit = 0. Take
measures such as polling the A/D conversion end interrupt request (INTAD) and removing the first conversion result.
(10) A/D conversion result register read operation
When a write operation is performed to the A/D converter mode register 0 (ADM0), analog input channel specification
register (ADS), and A/D port configuration registers 0, 1 (ADPC0, ADPC1), the contents of A/D conversion result
register may become undefined. Read the conversion result following conversion completion before writing to ADM0,
ADS, ADPC0, and ADPC1. Using a timing other than the above may cause an incorrect conversion result to be read.