Datasheet

78K0/Ix2 CHAPTER 11 A/D CONVERTER
R01UH0010EJ0500 Rev.5.00 387
Feb 28, 2012
Cautions 1. Make sure the period of <2> to <7> is 1  s or more.
2. If the timing of <2> is earlier than that of <6>, <2> may be performed any time.
3. When switching from timer trigger mode to software trigger mode, switch the operation mode
and input channel after stopping the A/D conversion operation (clearing (0) ADCS).
4. To select the internal voltage (1.2 V) as an analog input, set the ADCS bit to 1 when at least 10
 s
have elapsed after having set the V12SEL bit to 1 while the A/D conversion operation was
stopped (ADCS = 0).
Remark Two types of A/D conversion result registers are available.
 ADCRXn (16 bits): Store 10-bit A/D conversion value
 ADCRXnL (8 bits): Store lower 8-bit of A/D conversion value
Figure 11-16. Basic Operation of A/D Converter (Timer Trigger Mode)
Conversion time
Sampling time
Sampling
A/D conversion
Undefined
Conversion
result
A/D converter
operation
SAR
A/D conversion
result register
Conversion
result
INTAD
ADCS
A/D trigger signal
of TMXn (n = 0, 1)
A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register 0 (ADM0)
is reset (0) by software.
If a write operation is performed for the analog input channel specification register (ADS) during an A/D conversion
operation, the conversion operation will be initialized. If the ADCS bit is set (1), conversion is started from the beginning
after the A/D trigger signal of TMXn is detected.
Reset signal generation clears the A/D conversion result register (ADCRXn, ADCRXnL) to 0000H or 00H.
Remark n = 0, 1