Datasheet

78K0/Ix2 CHAPTER 11 A/D CONVERTER
R01UH0010EJ0500 Rev.5.00 377
Feb 28, 2012
(8) A/D port configuration registers 0, 1 (ADPC0, ADPC1)
ADPC0 switches the P20/AMP-/ANI0 to P27/ANI7 pins to digital I/O or analog input of port. Each bit of ADPC0
corresponds to a pin of port 2 and can be specified in 1-bit units.
ADPC1 switches the ANI8/P70 pin to digital I/O or analog input of port. Each bit of ADPC1 corresponds to a pin of
P70 in port 1 and can be specified in 1-bit units.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears ADPC0 and ADPC1 to 00H.
Remark A/D converter analog input pins differ depending on products.
 78K0/IY2: ANI0, ANI1, ANI3 to ANI5
 78K0/IA2: ANI0 to ANI5
 78K0/IB2: ANI0 to ANI8
Figure 11-11. Format of A/D Port Configuration Register 0 (ADPC0)
(1) 78K0/IY2
Address: FF2EH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
ADPC0 0 0 ADPCS5 ADPCS4 ADPCS3 0 ADPCS1 ADPCS0
(2) 78K0/IA2
Address: FF2EH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
ADPC0 0 0 ADPCS5 ADPCS4 ADPCS3 ADPCS2 ADPCS1 ADPCS0
(3) 78K0/IB2
Address: FF2EH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
ADPC0 ADPCS7 ADPCS6 ADPCS5 ADPCS4 ADPCS3 ADPCS2 ADPCS1 ADPCS0
ADPCSn Digital I/O or analog input selection (n = 0 to 7)
0 Analog input
1 Digital I/O
Cautions 1. Set the pin set to analog input to the input mode by using port mode register 2 (PM2).
2. If data is written to ADPC0, a wait cycle is generated. Do not write data to ADPC0 when the
peripheral hardware clock is stopped. For details, refer to CHAPTER 31 CAUTIONS FOR WAIT.