Datasheet

78K0/Ix2 CHAPTER 11 A/D CONVERTER
R01UH0010EJ0500 Rev.5.00 376
Feb 28, 2012
Figure 11-10. Format of Analog Input Channel Specification Register (ADS) (2/2)
ADS0ADS1ADS2ADS3 Analog input
channel
Input source
ANI0
ANI1
ANI2
Note 1
ANI3
ANI4
ANI5
ANI6
Note 2
ANI7
Note 2
ANI8
Note 2
PGA output
Note 3
Internal voltage (1.2 V)
P20/ANI0 pin
P21/ANI1 pin
P22/ANI2 pin
Note 1
P23/ANI3 pin
P24/ANI4 pin
P25/ANI5 pin
P26/ANI6 pin
Note 2
P27/ANI7 pin
Note 2
P70/ANI8 pin
Note 2
PGA output signal
Note 3
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
V12SEL
0
0
0
0
0
0
0
0
0
1
ADOAS
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Setting prohibitedOther than above
A/D conversion start method selection
Note 4
Normal start (software trigger mode)
TMX0 synchronization (timer trigger mode set by A/D conversion trigger signal of TMX0)
TMX1 synchronization (timer trigger mode set by A/D conversion trigger signal of TMX1)
Setting prohibited
ADTRG1
0
0
1
1
ADTRG0
0
1
0
1
Notes 1. Setting permitted in 78K0/IA2 and 78K0/IB2.
2. Setting permitted in 78K0/IB2.
3. Setting permitted in products with operational amplifier.
4. Switching the A/D conversion start method should be done after stopping the A/D conversion operation
(clearing (0) ADCS).
Cautions 1. Set a channel to be used for A/D conversion in the input mode by using port mode registers 2
and 7 (PM2, PM7).
2. Set ADS after PGA operation setting when selecting the PGA output signal as analog input. Set
ADS after single AMP operation setting when selecting the operational amplifier output signal as
analog input (refer to CHAPTER 12 OPERATIONAL AMPLIFIER).
3. To select the internal voltage (1.2 V) as an analog input, set the ADCS bit to 1 when at least 10
 s
have elapsed after having set the V12SEL bit to 1 while the A/D conversion operation was
stopped (ADCS = 0).
4. If data is written to ADS, a wait cycle is generated. Do not write data to ADS when the peripheral
hardware clock (f
PRS) is stopped. For details, refer to CHAPTER 31 CAUTIONS FOR WAIT.